The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for validating cache coherency protocol within a processor.
Modern processors employ multiple levels of cache to reduce demands of increasing memory bandwidth. Of these levels of cache, Level 3 (L3) cache and Level 2 (L2) cache typically are shared among instructions and data, while Level 1 (L1) cache is kept separate for instructions and data. Therefore, coherency hardware is incorporated into the modem processors to keep L1 Instruction cache (L1 I-Cache) and L1 Data Cache (L1 D-Cache) portions of the L1 cache coherent. Thus, it is of paramount importance that the I-Cache and D-Cache of a processor be kept coherent, which requires internal cache synchronization techniques that detect modifications to lines that are shared by the I-side and D-side caches to keep both the cache copies coherent. Validation of such coherency in post silicon validation is a difficult task and, to date, there have been no effective mechanisms that validate such coherency.